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These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

The proposed TMR code generator for implementing the FPGA design is also described.

Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The overview of the most standard techniques used for FPGA designs is described in the paper. Fault-tolerant techniques can detect the faults and correct them, or mask the faults. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. The primary objective of any fault tolerance technique is to produce a dependable system. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. FPGA designs are also critical to errors and failures due to radiations. The FPGA has been involved in many safety and mission-critical applications in the last few decades. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV Several flip-flop designs have been validated on IHP's 130,nm BiCMOS process, by irradiation of custom-designed shift registers.

The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications.